The recent advances in very deep sub-micron (VDSM) integrated circuits (ICs) have brought new challenges in the physical design methodology process of integrated systems. In modern electronic circuits, geometries become smaller; clock frequencies increase; and on-chip interconnections gain increased importance in the prediction of performance.
Conventional electronic circuit design tools focus on post-layout verification of the layout when the physical design of the entire chip design is complete and detailed information about the parasitics of the physical designs and the currents drawn by the transistors are known. In other words, conventional circuit synthesis step is followed by layout synthesis and each step is carried out independent of the other. This is again followed by a physical or formal verification step to check whether the desired performance goals have been achieved after layout generation and extraction. These steps are carried out iteratively in such conventional approaches till the desired performance goals are met. These conventional approaches basically perform post-layout verification on the complete layout, identify the problems, modify the layout, perform simulation(s) again with the modifications to ensure various goals are met, and re-perform the post-layout verification again to see, for example, if all design rules are fulfilled. Nonetheless, such conventional approaches waste a lot of computing resources in this iterative approach.
Therefore, what is needed is a method, a system, and a computer program product for implementing incremental extraction based simulation for electronic circuit designs.